The scaling of Metal-Oxide-Semiconductor (MOS) or Metal-Insulator-Semiconductor (MIS) transistor devices has reached a point where the length of the gate electrode is only a few tens of nanometers. Requirements for the source/drain extensions (the ultra-shallow junctions USJ) are mainly three-fold, i.e. very high activation (for end-of-the-roadmap devices above the solid solubility limit), ultra-shallow (towards less than 10 nm) and a very high lateral abruptness (1–2 nm/decade). The last one is also dictated by another requirement, the gate leakage level at the junction's overlap with the gate region. There is a trade-off between having no overlap for minimal gate leakage and enough overlap for optimal gate action on the junction. This trade-off is one of the major problems in scaling down the planar devices.
In U.S. Pat. No. 6,274,446 a method is described for the fabrication of a semiconductor device comprising abrupt source/drain extensions with controllable gate electrode overlap. The method comprises the steps of forming a gate structure on a semiconductor substrate, followed by forming an oxide layer on the gate and substrate. First, sidewall spacer regions are formed on the sides of the gate structure. Deep source/drain regions that do not overlap with the gate electrode are implanted in the semiconductor substrate. In order to create overlap, second spacer regions of silicon are formed on the sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided in order to electrically connect them. Also portions of source/drain extension regions in the semiconductor substrate adjacent the gate structure are silicided.
A first disadvantage of the method described in the above document is the number of extra steps required, i.e. “extending” the gate electrode by means of depositing silicon side wall spacers, etching back the spacers and connecting the spacers to the body of the original gate electrode.
Another disadvantage of the above method is that by the inevitable presence of an oxide layer between the body of the gate electrode and the silicon sidewall spacers, the overall gate electrode is in fact a discontinuous body of material with deleterious effects on the properties thereof.
In EP 1 089 344 an insulated gate field effect transistor and a method of making the same are described. The device comprises a first gate insulating film, such as TiO2, which is formed on a channel region. A gate electrode is formed on the first gate insulating film. Source and drain regions are formed in a surface portion of a p-well region. The gate electrode is formed such that it may partially overlap the source/drain region. The TiO2 film is subjected to either isotropic or anisotropic etching so that a portion of the TiO2 film which lies on the source/drain region, may be removed, hereby forming a recess underneath the gate electrode.
In JP 11 163323 a semiconductor device comprising an insulating layer, a gate electrode and a source and drain is described. By adjusting the etching time of an etching process of the insulating layer, the overlap length between the gate electrode and the source and drain can be adjusted. Etching of the insulating layer is performed by wet chemical etching in a 0.3% HF solution.
A disadvantage of EP 1 089 344 and JP 11 163323 is that the etching process of the insulating layer can not be controlled very well. Nowadays, scaling down of electric and electronic devices plays a very important role in semiconductor processing. With the methods described in EP 1 089 344 and JP 11 163323 it will be difficult to form, in a controllable way, shallow recesses in devices having small dimensions.